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overview the cla70000 gate array family is gec plessey semiconductors' (gps?) sixth generation cmos gate array product. the family consists of nine arrays implemented on the latest generation (1 micron) twin well epitaxial cmos process. the process in conjunction with the advanced layout and route software, offers extremely high packing densities. the array architecture is based upon the earlier well proven cla60000 series with the emphasis being placed on high speed, high packing density, and provision of comprehensive cell libraries. the cell libraries encompass new dsp and other specialized macros. full design support is available for major industry standard asic design software tools, as well as gec plessey semiconductor? proprietary pds2 design environment. design support is provided by gec plessey semiconductor? design centers, each offering a variety of design routes, which may be customized to individual customer requirements. product details the cla70000 array series is shown below with typical figures given for usable gates. actual gate utilization is dependent on circuit structure, giving a range of 40 -70% for two layer metallisation. cla70000 series high density cmos gate arrays march 1992 recent advances in cmos processing technology and improvements in design architecture have led to the development of a new generation of array-based asic products with vastly improved gate integration densities. this family of cla70000 1 micron cmos arrays brings considerable advantages to the design of next generation systems combining high performance and high complexity. features n low power channelless arrays from 5,000 to 250,000 available gates (5 m w / gate / mhz) n 1 micron (0.8 micron effective) twin well epitaxial process n typical gate delays of 400 ps (nand2 , fanout=2) n comprehensive cell library including dsp, jtag/bist and compiled memory cells (rom blocks to 64k bits and ram blocks to 16k bits) n extensive range of plastic and ceramic packages for both surface mount and through board assembly n flexible i/o structure allows user to define power pad locations n fully supported on industry standard workstations and in-house software n high drive output stages with slew rate control n supports jtag and bist test philosophies (ieee 1149-1 test procedures) n mil 883c compliant product available (paragraph 1.2.1) device number cla70000 cla71000 cla72000 cla73000 cla74000 cla75000 cla76000 cla77000 cla78000 i/o and power pads 44 68 84 100 120 160 200 256 304 gate complexity 5k 12k 19k 27k 39k 70k 110k 182k 256k estimated usable gates 2.5k 6k 9.5k 13.5k 17.5k 31.5k 49.5k 82k 115k 2462 - 3.1 (supersedes january 1992 edition - version 2.1)
vss supply vss supply programmable contacts fig 1. diagrammatic representation of array core cell core cell arrangement n supports compact macros n allows high density routing a four transistor group (2 nmos and 2 pmos) (fig.1) forms the basic cell of the core array. this array element is repeated in a regular fashion over the complete core area to give an homogenous ?ull field?(sea of gates) array. this lends itself to hierarchical design, allowing pre-routed user defined subcircuits to be repeated anywhere on the array. the core cell structure together with all associated cell libraries have been carefully designed to maximize the number of nets which may be routed through the cell. this enables optimal routing of both data flow and control signal distribution schemes thus giving very high overall utilization factors. this feature is of particular benefit in designs using highly structured blocks such as memory or arithmetic functions. i/o buffer arrangement n several hundred different i/o cell combinations n programmable slew rate control on all outputs n excellent latchup and esd immunity the i/o buffers are the interface to external circuitry and are therefore required to be robust and flexible. both inputs and outputs incorporate electrostatic discharge (esd) protection structures which can withstand in excess of 2kv, and are highly resistant to latch-up due to the epitaxial process. in addition the construction concepts used for the i/o cells provide the designer with several hundred different options of i/o cell configuration. the cla70000 i/o buffers (fig.2) contain all the components for static protection, cmos and ttl compatible input stages, and a wide variety of intermediate and output drive configurations. included are schmitt triggers, tristate controls, and slew rate controlled output buffers. all i/o buffer locations can be configured as supply pads (vdd and vss). slew rate control of output drivers is a useful feature when multiple high drive outputs need to be switched simultaneously, as may occur on driving capacitive loads such as buses. using regular output buffers with their inherently fast edge speed can lead to significant power supply noise transients, with possible mis-operation as a result. to overcome this problem. the cla70000 family includes a set of slew rate controlled output drivers, which use proprietary design techniques to control the turn-on of the output transistors (di/dt). these cells provide a significant benefit in the trade off between switching current magnitude and the number of supply pads required. fig 2. slew control & i/o block vdd supply vss supply ip op1 op2 ib1 ib2 bonding pad pin opt3 p n p n d input data 2.5 volts 2.5 volts 50 pf ibsk1, ibsk2 and ibsk3 have been characterised to g ive the correct timin g when connected to the opt* cells. slew rate controlled driver i/o block i/o block slew rate control ib3 ib4 ib5
power supply distribution n three power rings for good noise immunity n optimized for efficient routing n user defined placement of power and ground pads the power supply distribution scheme for the cla70000 arrays (fig.3) has the flexibility to meet varying applications needs. three separate power rings are used, one each for the internal core logic, intermediate buffer cells, and large output driver cells. noise generated in the low impedance output drivers is isolated from the core logic and buffer areas. the distribution of the supply rails can be automatically positioned by the layout software which allows greater design flexibility and optimisation. the power supply rings may be connected either to separate pad locations or combined at a single location. all i/o cell pads may be configured as either power or ground, giving complete flexibility to the designer. process technology n advanced 1 micron twin well process with epitaxial substrate n class 10 six inch wafer fabrication facility n high density low power process fig 3. power supply organisation recommended maximum operating limits parameter min max units supply voltage 3.0 5.5 v input voltage vss vdd v output voltage vss vdd v operating temperature commercial grade 0 70 c industrial grade -40 85* c military grade -55 125** c * 125 c maximum junction temperature for plastic devices. **subject to a maximum junction temperature of 150 c for ceramic devices. absolute maximum ratings parameter min max units supply voltage -0.5 7.0 v input voltage -0.5 vdd + 0.5 v output voltage -0.5 vdd + 0.5 v esd protection 2.0 k volts current per pad 100 ma storage temperature ceramic -65 150 c plastic -40 125 c operation outside these absolute maximum ratings may permanently damage device characteristics and may affect reliability. vss } supply to vdd } intermediate buffers vdd } supply to vss } i/o buffers supply to core logic the cla70000 arrays are built using the gec plessey 1 micron drawn cmos process, which is the third generation of our ??series process family. manufacture is at gps? class10, 6-inch fabrication facility. the process is a twin well, self aligned oxide-isolated technology on an epitaxial substrate, with an effective channel length of 0.8 micron, giving low defect density, high reliability, and inherently low power dissipation. the process has excellent immunity to latchup, and esd, and exhibits stable performance characteristics ideal for all commercial, industrial and military applications.
manufacturing facility n computer aided manufacturing n digital testers with large pinout capacity n vibration free for reliable manufacture the cla70000 product is manufactured near plymouth, england in the latest purpose built facility for sub-micron process geometries. the factory uses the latest automated equipment for 6 inch wafers and computer aided manufacturing techniques to ensure production efficiency. wafer fabrication is carried out in class 10, or better, clean room conditions in a vibration free environment to assure the lowest possible defect level. in addition to the world class wafer facility there are excellent probe and final test areas equipped with the latest analog and digital testers capable of handling complex test vectors and large pinouts. this large investment shows gec plessey semiconductors commitment to all the market areas needing state-of-the-art cmos asics. cell library n comprehensive range of cells n specialized dsp and bist sub-libraries n compatible with megacell and cla60000 a very comprehensive cell library is available for the cla70000 series. it contains sub libraries which may be used in specific applications areas such as digital signal processing (dsp) and built in self test (bist). more details on these specialized libraries can be found in applications notes or the design manual. the 1.4 micron (drawn) cmos array (cla60000) cell library may be converted to the equivalent cells on the cla70000 to allow system upgrades. equivalent cells are also available for the corresponding mva70000 megacell to enable an easy transition to a standard cell product to minimize silicon area or to add analog functions. cell library logic array cells buf buffer driver st1 schmitt trigger delay delay cell 2inv dual driver inv2 inverter, dual drive inv4 inverter, quad drive inv8 inverter, octal drive nand2 2 input nand gate nd3 3 input nand gate nand3 3 input nand gate + inverter 2nand3 dual 3 input nand gate nand4 4 input nand gate nand5 5 input nand gate nand6 6 input nand gate nand8 8 input nand gate nor2 2 input nor gate nr3 3 input nor gate nor3 3 input nor gate + inverter 2nor3 dual 3 input nor gate nor4 4 input nor gate nor5 5 input nor gate nor6 6 input nor gate nor8 8 input nor gate a2o21 2 input and to 2 input nor gate + inverter o2a21 2 input or to 2 input nand gate + inverter 2a2o21 dual 2 input and to 2 input nor gate 2o2a21 dual 2 input or to 2 input nand gate 2anor 2 input ands to 2 input nor gate 2onand 2 input ors to 2 input nand gate a2o31 2 input and to 3 input nor gate o2a31 2 input or to 3 nand gate a3o21 3 input and to 2 input nor gate o3a21 3 input or to 2 input nand gate a4o21 4-input ands to 2 input nor gate o4a21 4-input ors to 2 input nand gate a2041 2-input and to 4 input nor gate o2a41 2-input ors to 4 input nand gate 3a2o31 3 2-input ands to 3 input nor gate 3o2a31 3 2-input ors to 3 input nand gate o2a2o21 2 input or to 2 input and to 2 input nor gate a2o2a21 2 input and to 2 input or to 2 input nand gate exor exclusive or gate + nand gate + inverter exnor exclusive nor gate + nor gate + inverter exor2 2 input exclusive or gate exnor2 2 input exclusive nor gate ex2 exclusive or gate + inverter exn2 exclusive nor gate + inverter exor3 3 input exclusive or gate exnor3 3 input exclusive nor gate exprim 2 input exclusive or gate primitive hadd half adder + inverter sum sum block sum2 sum block carry carry block + nor gate carry2 carry block + inverter fadd full adder + nor gate bmf1 full adder 1 bmf2 full adder 2 mux2to1 2 to 1 multiplexer mux4to1 4 to 1 multiplexer mux8to1 8 to 1 multiplexer muxi2to1 2 to 1 inverting multiplexer
muxi4to1 4 to 1 inverting multiplexer muxi8to 1 8 to 1 inverting multiplexer clka basic clock driver 2clka dual basic clock driver clkap basic clock driver + inverter clkam basic clock driver + inverter clkb large clock driver + inverter clkbp large clock driver + inverter clke1 clock driver with enable clke2 clock driver with enable clke3 clock driver with enable tm buffered transmission gate 2tm transmission gate for 2 to 1 multiplexing bdr internal bus driver dl data latch dl2 data latch dlrs data latch with set and reset dlars data latch with set and reset df master-slave d type flip flop dfrs master-slave d type flip flop with set & reset mdf multiplexed master-slave d type flip flop mdfrs multiplexed master-slave d type flip flop with set & reset m3df multiplexed m/s d type flip flop m3df multiplexed m/s d type flip flop with set & reset jk j-k flip-flop jkrs j-k flip-flop with set & reset jbark jbar-k flip-flop jbarkrs jbar-k flip-flop with set & reset bdl buffered data latch bdlrs buffered data latch with set & reset jbarkrs buffered data latch with set & reset bdf buffered master-slave d type flip-flop bdfrs buffered master-slave d type flip-flop with set & reset bmdf buffered mux. master-slave d type flip-flop bmdfrs buffered mux. m/s d type with set & reset bjbark buffered j-k flip-flop bjbarkrs buffered j-k flip-flop with set & reset trid tristate driver gnd ground cell vdd vdd cell intermediate buffer cells ibccmos1 cmos input buffer + large 2 input nand gate ibccmos2 cmos input buffer + data latch ibttl1 ttl input buffer + large 2 input nand gate ibbtl2 ttl input buffer + data latch ibst1 input schmitt buffer with cmos switching levels ibst2 input schmitt buffer with 2v switching levels ibgate nand2/nor2 gates ibclkb large clock driver ibdf master-slave d type flip flop ibdfa master-slave d type flip flop ibsk1 driver with slewed outputs ibsk2 driver with slewed outputs ibsk3 driver with slewed outputs ibtrid tri-state driver ibtrid1 tri-state driver with slewed outputs + 2 inverters ibtrid2 tri-state driver with slewed outputs + 2 inverters ibtrid3 tri-state driver with slewed outputs + 2 inverters ib2bd dual high powered inverters drv3 clock driver drv6 clock driver pad input cells ipnr input cell with no pull up or down resistors ipr1p input cell with 1kohm pull up resistor ipr1m input cell with 1kohm pull down resistor ipr2p input cell with 2kohm pull up resistor ipr2m input cell with 2kohm pull down resistor ipr3p input cell with 4kohm pull up resistor ipr3m input cell with 4kohm pull down resistor ipr4p input cell with 75kohm pull up resistor ipr4m input cell with 75kohm pull down resistor oscillator cells (crystal) to be defined pad output cells op1 smallest drive output cell op2 small drive output cell op3 standard drive output cell op6 medium drive output cell op12 large drive output cell op5b standard drive non-inverting output cell op11b large drive non-inverting output cell opt1 smallest drive tri-state output cell opt2 small drive tri-state output cell opt3 standard drive tri-state output cell opt6 medium drive tri-state output cell opt12 large drive tri-state output cell op4b standard drive non-inverting tri-state output cell op10b large drive non-inverting tri-state output cell opod1 smallest drive open-drain output cell opod2 small drive open-drain output cell opod3 standard drive open-drain output cell opod6 medium drive open-drain output cell opod12 large drive open-drain output cell
testcontrol cells jtap pds bist jtag interface controller jtclk pds-bist clock gating and buffer cell jtidreg pds-bist jtag identification register test register component cells jtdut test register data bit (transparent) with update latch jtduf test register data bit (transparent)] with update latch jtddt test register data bit (transparent) jtddf test register data bit (transparent) jtcut test register data bit (clocked) with update latch jtcuf test register data bit (clocked) with update latch jtcdt test register data bit (clocked) jtcdf test register data bit (clocked) jtct test register local controller jtbf16 test register driver 4-19 databits jtbf16 test register driver 20-34 databits cla70000 dsp macrocell library ripple carry adders adr1 1bit adder adr3 4 bit adder adr8 8 bit adder adr16 16 bit adder adr24 24 bit adder adr32 32 bit adder high speed carry select adders ads1 1bit adder ads3 4 bit adder ads8 8 bit adder ads16 16 bit adder ads24 24 bit adder ads32 32 bit adder carry select adders (reduced area) adt8 8 bit adder adt16 16 bit adder adt24 24 bit adder opod5b standard drive non-inverting open-drain output cell opod11b large drive non-inverting open-drain output cell opos1 smallest drive open-source output cell opos2 small drive open-source output cell opos3 standard drive open-source output cell opos6 medium drive open-source output cell opos12 large drive open-source output cell opos5b standard drive non-inverting open-source output cell opos11b large drive non-inverting open-source output cell power supply cells opvp vdd power pad (outputs) opvm gnd power pad (outputs) opvpb vdd power pad (outputs) : break in vdd opvmb gnd power pad (outputs) : break in gnd opvpbb vdd power pad (outputs) : break in vdd & gnd opvmbb gnd power pad (outputs) : break in vdd & gnd ibvp vdd power pad (buffers) ibvm gnd power pad (buffers) ibvpb vdd power pad (buffers) : break in vdd ibvmb gnd power pad (buffers) : break in gnd ibvpbb vdd power pad (buffers) : break in vdd & gnd ibvmbb gnd power pad (buffers) : break in vdd & gnd lavp power pad for logic array lavm | lagnd | lavdd | cla70000 pds-bist (jtag/ieee1149-1) library test register cells jtrdu4,8,16,24,32 4,8,16,24,32 bit transparent test registers with update latches jtrdd4,8,16,24,32 4,8,16,24,32 bit transparent test registers jtrcu4,8,16,24,32 4,8,16,24,32 bit clocked test registers with update latches jtrcd4,8,16,24,32 4,8,16,24,32 bit clocked test registers
adt32 32 bit adder subtractor blocks adsu4 4 bit subtractor add-on adsu8 8 bit subtractor add-on adsu16 16 bit subtractor add-on adsu24 24 bit subtractor add-on adsu32 32 bit subtractor add-on shifters arithmetic right (padded with msb) sha4 4 stage arithmetic right shifter sha8 8 stage arithmetic right shifter sha16 16 stage arithmetic right shifter sha24 24 stage arithmetic right shifter sha32 31 stage arithmetic right shifter shifters barrel right (padded with lsb data exiting shifter) shb4 4 stage barrel right shifter shb8 8 stage barrel right shifter shb16 16 stage barrel right shifter shb24 24 stage barrel right shifter shb32 31 stage barrel right shifter shifters logic right/left (padded with zero's) shl4 4 stage logic right shifter shl8 8 stage logic right shifter shl16 16 stage logic right shifter shl24 24 stage logic right shifter shl32 31 stage logic right shifter logic units (8 function) fglo4 4 logic bit unit fglo8 8 logic bit unit fglo16 16 logic bit unit fglo24 24 logic bit unit fglo32 32 logic bit unit arithmetic units (8 function) fgar4 4 bit logic unit fgar8 8 bit logic unit fgar16 16 bit logic unit fgar24 24 bit logic unit fgar32 32 bit logic unit cla70000 dsp macrocell library multipliers and associated cells bma8x8 mixed mode multiplier (8 x 8 bits) bma16x16 mixed mode multiplier (16 x 16 bits) bma24x24 mixed mode multiplier (32 x 32 bits) bmb16x12 single pipeline multiplier (16 x 12 bits) bmc24x24 mixed mode multiplier (24 x 24 bits) bthe1 booth encoder bthd1 non-inverting booth decoder bthd2 inverting booth decoder many of the macro functions perform similar functions to the standard ttl and cmos logic families. the user is warned, however, that the logic functions may differ slightly and is therefore recommended to refer to the design manual rather than assume an exact functional copy. the pds simulator uses the constituent microcell models for circuit analysis. the macrocells are constructed from basic microcells and are placed and routed to give optimum use of chip area. macro function adders ada4 4 bit binary full adders with fast carry adg4 look ahead carry generator counters cna4 bcd counter/4 bit latch decoder/driver cnb4 4 bit counter latch cnc4 4 bit synchronous counter cnd4 4 bit binary up/down synchronous counter cnd4a 4 bit binary up/down counter with reset cne4 4 bit decade counter cnf4 4 bit binary synchronous counter cng4 4 bit binary counter decoders dra3t8 3 line to 8 line decoder/demultiplexer dra4t16 4 line to 16 line decoder/demultiplexer dra4t16a 4 line to 16 line decoder/demultiplexer no enable drb3t8 3 line to 8 line decoder/demultiplexer with address registers drb3t8 3 line to 8 line decoder/demultiplexer with address latches drd2t4 2 line to line decoder drf4t10 4 line to 10 line bcd decoder drg4t10 4 line to 10 line excess 3 to decimal decoder drh4t10 4 line to 10 line excess gray to decimal decoder decoder dri10 bcd to decimal decoder/driver drj7 bcd to 7 segment decoder/driver drk7 bcd to 7 segment decoder/driver
srb8 2 bit piso shift register with clear srb8a 2 bit piso shift register without clear src8 8 bit piso shift register with clear srd4 8 bit sipo shift register with clear sre4 4 bit pipo shift register with jkbar input srf8 8 bit shift and store register with tristate outputs srg4 4 bit bidirectional universal shift register srj4 4 bit parallel access shift register srk5 5 bit shift register process monitor perf performance monitor bist * rgbit test register (one bit) rgtbit test register (one monitor bit) rgdiag diagnostic control unit rgctl test register controller rghold test register hold circuitry * (early built in self test cells) see cla7bist library cla70000 paracell library memory cells rbram ram max 16384 bits per block words 2:128, bits 1:128 (min:max) rorom rom max 65536 bits per block words 2:2048, bits 2:64 (min:max) drl7 bcd to 7 segment decoder/driver encoders ena8t3 8 line to 3 line priority encoder enb10t4 10 line to 4 line priority encode flip-flop ffa8 8 bit bistable latches ffb6 6 bit d-type flip-flop with clear ffc4 4 bit d-type flip-flop with clear & complimentary outputs ffd8 octal d-type flip-flop with clear alu/functional generator fga5 4 bit alu/function generator adders mca4 4 bit magnitude comparators multipliers mla10 decade rate multiplier mlb4x4 4 by 4 binary multiplier with tristate outputs mlw7 7 bit wallace trees with tristate outputs multiplexers mxa8t1 8 line to 1 line data selector / multiplexer mxb4t1 dual 4 line to 1 line data selector / multiplexers mxb4t1a dual 4 line to 1 line data selector / multiplexer with inverted tristate outputs mxc2t1 quad 2 to 1 data selector / multiplexers mxc2t1a quad 2 to 1 selector (inverted outputs) mxd4t1 4 to 1 multiplexor with strobe mxe4t1 4 to 1 multiplexor with strobe mxf2t1 2 to 1 multiplexeor with storage parity generator pga9 9 bit odd/even parity generator/checker shift registers sra2 2 bit pos shift register with clear sra4 4 bit pos shift register with clear sra8 8 bit sipo shift register with clear sra8a 8 bit sipo shift register without clear srb2 2 bit piso shift register with clear srb4 4 bit piso shift register with clear
design support and interfaces n flexible design route approach n design center engineer assigned to every customer circuit n full turnkey service capability design and layout support for cla70000 arrays is available from various centers worldwide each of which is connected to our headquarters via high speed data links. a design center engineer is assigned to each customer? circuit, to ensure good communication , and a smooth and efficient design flow. it should be noted that sign-off simulation against the gps 'golden' simulator is also supported at our local design centers. gps offers a variety of formal design routes as illustrated in the table below. differing interface methods allow for varying levels of involvement in a manner which complements individual customer design styles, whilst maintaining our responsibility to ensure first time working devices. as part of the design process gps operates a thorough design audit procedure to verify compliance with customer specification and to ensure manufacturability. the procedure includes four separate review meetings, with the customer, held at key stages of the design. review 1: held at the beginning of the design cycle cad support design routes to check and agree on all performance, packaging, specifications and design timescales. review 2: held after logic simulation but prior to layout checks to ensure satisfactory functionality, timing performance, and adequate fault coverage. review 3: held after layout and post layout simulation verification of satisfactory design performance after insertion of actual track loads. final check of all device specifications before prototype manufacture. review 4: held after prototype delivery confirm that devices meet all specifications and are suitable for full scale production. design tools the focus of the gec plessey design tool methodology is that of maintaining an open cad system with all interfaces standardized via edif 2.0 . this enables us to provide full support for a variety of 3rd party asic design tools and facilitates rapid updating of associated libraries. it also provides an interface to the gec plessey (pds2) design system, which offers a total design environment including behavioral and functional level modelling. third party software pds in-house software turnkey service options design review 1 schematic capture customer customer gps logical design customer customer gps design review 2 physical design gps customer or gps gps design review 3 prototype manufacturing gps gps gps prototype evaluation customer customer customer design review 4 production gps gps gps
pds2 - the gps asic design system n behavioral, functional, and gate level modelling n vhdl and third party links n supports hierarchical design techniques n edif 2.0 interface pds2 is gps? own proprietary asic design system. it provides a fully-integrated, technology independent vlsi design environment for all gps cmos semicustom products. pds2 runs on digital equipment computers and is self configuring according to the available machine resources. it comprises design capture (schematic capture or vhdl), testability analysis, logic simulation, fault simulation, auto place and route, and back annotation. the system offers full support for hierarchical design techniques, maintained from design capture through to layout, as well as advanced design management tools. pds2 may be used either at a gps design center or under licence at the customer? premises. a three day training course is available for first time users. third party software support n design kits for major industry standard asic design software tools n all libraries include fully detailed timing information n edif 2.0 interface n post layout back annotation available gps supports a wide range of third party design tools including ikos, mentor, verilog, and viewlogic at the time of printing. please check with our sales offices for the most recent additions. the design kits offer fully detailed timing information for all cell libraries, netlist extraction utilities, and post layout back annotation capability where applicable. an example of a workstation design flow is shown in fig 5 below. please contact your local gec plessey semiconductor? sales office for further information about support of particular tools. fig 5. workstation design flow specifications thermal management n lower power cmos for better thermal management n improved reliability n power packages available the increase in speed and density available through cmos process geometry reduction, results in a corresponding increase in power dissipation. semicustom designers now have the ability to design circuits of 100,000 gates and over, and chip power consumption is (or should be) a very important concern. the logic core of 100k plus gates is the dominant factor in power dissipation at this complexity. it is essential to offer ultra low power core logic to maintain an acceptable overall chip power budget. to minimize this problem gps? cla70000 arrays offer low power factors and a selection of power packages. dissipation of 5 m w per gate per mhz gate power and 1 m w per gate load, is lower than most competitive arrays, with the reduced junction temperatures having the added advantage of improved performance and reliability. cla70000 power dissipation calculation cla70000 series power dissipation for any array can be estimated by following the example (calculated for the cla76xxx) below. number of available gates 110112 assume percent gates used 40% number of used gates (110102 x 0.4) 44045 assume 15% of gates switching during. each clock cycle (44045 x 0.15) 6607 power dissipation/gate/mhz (gate fanout typically 2 loads) 7 m w total core dissipation/mhz (6607 x 0.007) 46.2 mw number of available i/o pads 200 percent of i/o pads used as outputs 40% number of i/o pads used as outputs 80 number of output buffers switching each clock cycle (20%) 16 dissipation/output buffers/mhz/pf 25 m w output loading 50 pf power/output buffer/mhz 1.25mw total output buffer dissipation/mhz 20mw total power dissipation/mhz 66.2mw estimated dissipation of the circuit at the frequencies below is total power at 10 mhz clock rate 0.66w total power at 25mhz clock rate 1.65w schematic capture test vector generation simulation vector translation back - annotation erc & netlist translation schematic symbols cla libraries simulation models mle place & route design verification test program generation pds environment workstation environment
140 90 40 -10 -60 0 0.2 0.4 0.6 0.8 1 1.2 1.4 normalised delay multiplier vs temperature delay multiplier (normalised to 25?) temperature ? normalised delay multiplier vs voltage 4 4.5 3.5 5 5.5 3 0.8 1 1.2 1.4 1.6 delay multiplier (normalised to 5v) voltage ac characteristics for selected cells the cla70000 technology library contains all the timing information for each cell in the design library. this information is accessible to the simulator, which calculates propagation delays for all signal paths in the circuit design. the simulator can automatically derate timings according to the various factors such as: supply voltage variation (from nominal 5v) junction temperature processing tolerance - manufacturing spreads gate fanout - logic loading on gate outputs interconnection wiring - net loading on gate outputs fig 6. fig 7. for initial assessments of feasibility, path delay multipliers can be estimated by referring to the following graphs in conjunction with the appropriate delays in the tables.
typical worst case propagation delay (ns) intermediate buffer cells propagation commercial industrial name cells description symbol delay (ns) fanout fanout fanout =2 2424 ibgate - large 2 input nand gate +2 input nor tplh 0.34 0.88 1.02 0.92 1.02 tphl 0.27 0.71 0.84 0.75 0.88 ibdf - master slave d-type tplh 0.48 1.24 1.44 1.30 1.50 flip-flop tphl 0.50 1.31 1.42 1.37 1.49 ibcmos1 cmos input buffer tplh 0.60 1.58 1.68 1.65 1.75 with 2 input nand gate tplh 0.45 1.17 1.21 1.22 1.27 - ac characteristics typical worst case propagation delay (ns) internal core cells propagation commercial industrial name cells description symbol delay (ns) fanout fanout fanout =2 2424 inv2 1 invertor dual drive tplh 0.27 0.70 0.84 0.73 0.88 tphl 0.18 0.47 0.56 0.49 0.58 nand2 1 2-input nand gate tplh 0.39 1.01 1.29 1.05 1.35 tphl 0.30 0.79 1.04 0.82 1.09 nor2 1 2-input nor gate tplh 0.50 1.30 1.81 1.35 1.89 tphl 0.22 0.57 0.80 0.60 0.84 df 1 master slave tplh 0.54 1.40 1.60 1.46 1.68 d-type flip-flop tphl 0.55 1.44 1.55 1.51 1.62 worst case propagation delay (ns) output buffer cells name cells description symbol op3 - standard output buffer tplh 0.73 1.90 6.49 1.99 6.79 tphl 0.49 1.27 4.40 1.33 4.60 op6 - medium output buffer tphl 0.50 1.30 3.59 1.35 3.76 tplh 0.33 0.85 2.42 0.89 2.53 op12 - large output buffer tplh 0.38 0.99 2.14 1.04 2.24 tphl 0.25 0.66 1.50 0.69 1.56 typical propagation commercial industrial delay (ns) fanout fanout fanout =10pf 10pf 50pf 10pf 50pf note : commercial worst case is 4.5v, 70 c operating industrial worst case is 4.5v, 85 c operating
characteristic low level input voltage ttl inputs (ibttl1/ibttl2) cmos inputs (ibcmos1/ibcmos2) high level input voltage ttl inputs (ibttl1/ibttl2) cmos inputs (ibcmos1/ibcmos2) input hysterisis (ibst1) rising falling (ibst2) rising falling input current cmos/ttl inputs (without resistor) inputs with 1k ohm resistor inputs with 2k ohm resistor inputs with 4k ohm resistor inputs with 75k ohm resistor resistor values nominal (note2) high level output voltage all outputs smallest drive cell op1/opos1/opt1 low drive cell op2/opos2/opt2 standard drive cell op3/opos3/opt3 medium drive cell op6/opos6,opt6 large drive cell op12/opos12/opt12 low level output voltage all outputs smallest drive cell op1/opod1/opt1 low drive cell op2/opod2/opt2 standard drive cell op3/opod3/opt3 medium drive cell op6/opod6,opt6 large drive cell op12/opod12/opt12 tristate output leakage current output short circuit current standard output op3/opt3/opod3 (note 3) op3/opt3/opos3 operating supply current (per gate) (note4) input capacitance output capcitance bidirectional pin capacitance symbol v il v ih v t+ v t- v t+ v t- i in v oh v ol i oz i os i ddop c i c out c i/o typ. 3.09 1.89 1.72 1.10 5.00 2.50 1.25 66.00 v dd -0.05 v dd -0.50 v dd -0.50 v dd -0.50 v dd -0.50 v dd -0.50 v ss +0.05 0.20 0.20 0.20 0.20 0.20 135.00 75.00 1.00 5.00 5.00 7.00 dc electrical characteristics all characteristics at commercial grade voltage and temperature (note1) conditions v il to v ih v ih to v il v il to v ih v ih to v il v in =v dd or v ss v in =v dd or v ss v in =v dd or v ss v in =v dd or v ss v in =v dd or v ss i oh =-1.00 m a i oh =-2.00ma i oh =-4.00ma i oh =-6.00ma i oh =-12.00ma i oh =-24.00ma i ol =1.00 m a i ol =2.00ma i ol =4.00ma i ol =6.00ma i ol =12.00ma i ol =24.00ma v oh =v ss or v dd v dd =max v out =v dd v dd =max v out =ov any inputs (note 5) any outputs (note 5) any i/o pin (note 6) min. 2.00 v dd -1.00 -1.00 2.20 1.10 0.56 18.00 v dd -1.00 v dd -1.00 v dd -1.00 v dd -1.00 v dd -1.00 -1.00 67.00 37.00 units v v v m a ma ma ma m a v v m a ma m a/mhz pf pf pf max. 0.80 1.00 +1.00 11.00 5.50 2.75 275.00 0.40 0.40 0.40 0.40 0.40 1.00 270.00 150.00 notes 1) commercial grade is 0 - 70 c, 5v 10% power supply voltage 2) resistor value spreads (min-max): low value (rtyp 1k) 0.5-2k ohm high value (rtyp 4k) 2k-8k ohm low value (rtyp 2k) 1.0-4k ohm high value (rtyp 75k) 20k-250k ohm 3) standard driver output op3 etc. short circuit current for other outputs will scale. not more than one output may be shorted at a time for a maximum duration of one second. 4) excluding peripheral buffers. 5) excludes package leadframe capacitance or bi-directional pins. 6) excludes package.
key - available array / package combinations. 70 71 72 73 74 75 76 77 78 gp44 1734 1734 gp52 1751 1710 gp64 1756 1756 1755 gp80 1733 1733 1643 1643 gp100 1644 1644 1644 gp120 1730 1730 1729 gp144 1758 gp160 1715 1715 70 71 72 73 74 75 76 77 78 gg44 1735 1735 gg52 1800 1800 gg64 1773 1773 1773 gg80 1740 1740 1740 1771 gg100 1675 1675 1675 gg120 1736 1736 1737 gg144 1770 gg160 1769* 1769 plastic quad flat pack (gp) ceramic quad flat pack (gg) cla70000 array package guide packaging n wide range of surface mount and through board packages n ceramic equivalents to most plastic packages - for fast prototyping n ongoing commitment to new package development production quantities of the cla70000 family are available in industry-standard ceramic and plastic packages according the codes shown below. prototype samples are normally supplied in ceramic only. dc dilmon dual in line, multilayer ceramic. brazed leads metal sealed lid. through board dg cerdip dual in line, ceramic body, alloy leadframe, glass sealed, through board dp plasdip dual in line, copper or alloy leadframe, plastic moulded. through board ac p.g.a. pin grid array, multilayer ceramic. metal sealed lid. through board ac (p) power p.g.a. as above with cavity down and cu/w heat plate mp small outline (s.o.) dual in line, ?ullwing?formed leads. plastic moulded surface mount lc lcc leadless chip carrier. multilayer ceramic. metal sealed lid. surface mount hc leaded chip carrier quad multilayer ceramic. brazed j formed leads. metal sealed lid. surface mount gc leaded chip carrier quad multilayer ceramic. brazed leads. metal sealed lid. surface mount gc (p) power leaded chip carrier as above with cavity down, and cu/w heat plate hg quad cerpac quad ceramic body, ??formed leads. glass sealed. surface mount. gg ceramic quad flatpack quad ceramic body, ?ullwing?formed leads. glass sealed. surface mount. hp plcc quad plastic leaded chip carrier. ??formed leads. plastic moulded. surface mount gp pqfp plastic quad flat pack. ?ullwing?formed leads. plastic moulded. surface mount packaging options the package style and pin count information is intended only as a guide. detailed package specification are available from gps design centers on request. available packages are being continuously updated, so if a particular package is not listed, please enquire through your gps sales representative. - prototypes only
70 71 72 73 74 75 76 77 78 lc28 1450 1450 lc44 1454 1454 1365 lc68 1433 1433 lc84 1455 1455 70 71 72 73 74 75 76 77 78 hg28 1560 1560 hg44 1562 1562 1562 hg68 1564 1564 1564 hg84 1567 1567 70 71 72 73 74 75 76 77 78 hc28 1624 1624 hc44 1630 1630 1630 hc68 1625 1625 1621 hc84 1626 1626 70 71 72 73 74 75 76 77 78 mp16l 1575 mp20 1583 mp24 1587 mp28 1768 70 71 72 73 74 75 76 77 78 mc16 1697 mc20 1698 mc24 1699 mc28 1700 plastic small outline (mp) ceramic small outline (mc) plastic leaded chip carrier (hp) co-fired ceramic leaded chip carrier (hc) 70 71 72 73 74 75 76 77 78 hp28 1613 1613 hp44 1490 1490 1490 hp68 1659 1659 1659 hp84 1660 1660 ceramic leadless chip carrier (lc) glass sealed ceramic leaded chip carrier (hg) ceramic leaded chip carrier (gc) power ceramic leaded chip carrier (gc) 70 71 72 73 74 75 76 77 78 gc132 tbd 1662 gc172 1668 1669 1680 tbd gc196 1672 tbd tbd 70 71 72 73 74 75 76 77 78 gc132 tbd tbd 1763 gc172 tbd tbd 1762 tbd gc196 tbd 1739 tbd gc256 tbd tbd 70 71 72 73 74 75 76 77 78 dp16 1558 dp22 1513 1513 dp24 1516 1517 1517 dp28 1522 1522 1522 dp40 1524 1524 1525 dp48 1485 1485 1485 plastic dual in line (dp) ceramic dual in line (dc) 70 71 72 73 74 75 76 77 78 dc16 1427 dc22 1396 1396 dc24 1321 1321 1321 dc28 1348 1348 1348 dc40 1620 1620 1620 dc48 1470 1470 1470
this publication is issued to provide outline information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to the products or services concerned. the company reserves the r ight to alter without notice the specification, design, price or conditions of supply of any product or service. united kingdom: swindon, tel: (0793) 518000 tx: 449637 fax: (0793) 518411. oldham, tel: (061) 682 6844, tx: 666001 fax: (061) 688 7898. lincoln, tel: 0522 500500 tx: 56380 fax: 0522 500550. wembley, tel: 081 908 4111 tx: 28817 fax: 081 908 3801. united states of america: scotts valley, tel: (408) 438 2900 itt tx: 4940840 fax: (408) 438 5576. dedham, tel: (617) 320-9790. fax: (617) 320-9383. irvine, tel: (714) 455-2950. fax: (714) 455-9671. san jose, tel:(408) 433- 1030 fax: (408) 433-1033. australia: rydalmere, nsw, tel: 612 638 1888. fax: 612 638 1798. france: les ulis cedex, tel: (6) 446 23 45 tx: 602858f. fax: (6) 446 06 07. italy: milan, tel: (02) 33001044/45 tx: 331347 fax: (gr3) 2316904. germany: munich, tel: (089) 3609 06 0 tx: 523980. fax: (089) 3609 06 55. japan: tokyo, tel: (3) 839 3001. fax: (3) 839 3005. primary semi-custom design centres headquarters operations gec plessey semiconductors cheney manor, swindon, wiltshire sn2 2qw, united kingdom. tel: (0793) 518000 tx: 449637 fax: (0793) 518411 gec plessey semiconductors sequoia research park, 1500 green hills road, scotts valley, california 95066, united states of america. tel (408) 438 2900 itt telex: 4940840 fax: (408) 438 5576 customer service centres france & benelux les ulis cedex tel: (1) 64 46 23 45 tx: 602858f fax : (1) 64 46 06 07 germany munich tel: (089) 3609 06-0 tx: 523980 fax : (089) 3609 06-55 italy milan tel: (02) 33001044/45 tx: 331347 fax: (gr3) 316904 japan tokyo tel: (03) 3296-0281 fax: (03) 3296-0228 north america integrated circuits, scotts valley, usa tel (408) 438 2900 itt tx: 4940840 fax: (408) 438 7023. sos, microwave and hybrid products, farmingdale, usa tel (516) 293 8686 fax: (516) 293 0061. south east asia singapore tel: 2919291 fax: 2916455 sweden johanneshov tel: 46 8 7228690 fax: 46 8 7227879 united kingdom & scandinavia swindon tel: (0793) 518510 tx: 444410 fax : (0793) 518582 these are supported by agents and distributors in major countries world-wide. gec plessey semiconductors 1992 publication no. ps 2462 issue no. 3.1 march 1992 70 71 72 73 74 75 76 77 78 ac68 1462 1462 ac84 1479 1479 ac100 tdb 1480 ac120 1481 1466 ac132 1467 ac144 1483 ac180 1484 1469 tdb tdb ac257 tdb 1764 ceramic pin grid array (ac) power ceramic pin grid array (ac) 70 71 72 73 74 75 76 77 78 ac84 1692 ac144 tbd 1693 tbd ac208 tbd tbd tbd ` a common information management system is used to monitor the manufacturing of gps cmos and bipolar processes. all products benefit from the use of this integrated monitoring system throughout all manufacturing operations leading to high quality standards for all technologies. further information is contained in the quality brochure, available from gps sales offices. quality and reliability n statistical process control used in manufacture n regular sample screening and reliability testing n screening to mil and industrial standards available at gps, quality and reliability are built into the product by statistical control of all processing operations and by minimizing random uncontrolled effects in all manufacturing operations. process management involves full documentation of procedures, recording of batch-by-batch data, using traceability procedures and provision of appropriate equipment and facilities to perform sample screening and conformance testing on finished product.

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